1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capturing an address signal in response to a leading edge of a clock signal.
2. Description of the Background Art
In recent years, kinds of synchronous static random access memories (hereinafter referred to as synchronous SRAM) have increased in order to improve an operating frequency and a utilization efficiency of a bus. Synchronous SRAM is SRAM operating in synchronization with a clock signal. Synchronous SRAM is classified into a flow-through type and a pipe-line type according to a difference in read latency and again classified into an early-write type, a late-write type and a double-late-write type according to a difference in write latency.
FIG. 15 is a time chart showing read operations in flow-through type synchronous SRAM and pipe-line type synchronous SRAM. In FIG. 15, not only is an address signal ADD is inputted in synchronization with a rising edge of clock signal CLK, but a read command is also inputted by a control signal WE. Q(T) indicates a read data signal of the flow-through type and Q(PL) indicates a read data signal of the pipe-line type.
A difference in read latency is a difference in the number of cycles between when address signal ADD and a read command are inputted and when a data signal Q corresponding to address signal ADD is outputted. That is, in a case of the flow-through type, a corresponding data signal Q(A0) is outputted in a cycle 0 in which an address signal (for example, A0) is inputted, whereas in a case of the pipe-line type, corresponding data signal Q(A0) is outputted in a cycle 1 subsequent to cycle 0 in which address signal A0 is inputted.
FIG. 16 is a time chart showing write operations in early-write type synchronous SRAM, late-write type synchronous SRAM and double-late-write type synchronous SRAM. In FIG. 16, not only is address signal ADD is inputted in synchronization with a rising edge of clock signal CLK, but a write command is inputted by control signal WE. D(EW), D(LW) and D(DLW) indicate write data signals of the early-write type, the late-write type and the double-late write type, respectively.
A difference in write latency is a difference in the number of cycles between when address signal ADD and a write command are inputted and when a data signal D corresponding to address signal ADD is inputted. That is, in a case of the early-rate type, a corresponding data signal D(A0) is inputted in the same cycle 0 as input cycle 0 in which an address signal (for example, A0) is inputted, whereas in a case of the late-write type, a corresponding data signal D(A0) is inputted in a cycle 1 subsequent to input cycle 0 in which address signal A0 is inputted. In a case of the double-late-write, a corresponding data signal D(A0) is inputted in a cycle subsequent to a cycle 2 again subsequent to input cycle 0 in which address signal A0 is inputted.
In a case where the late-write scheme or the double-late-write scheme is adopted, if a write operation and a read operation are alternately performed, two address signals A0 and A1 consecutively inputted, when being different from each other, cause no problem, whereas two address signals A0 and A1, when being the same as each other, cause an inconvenience that a data signal is read from a memory cell to which no data signal D has not yet been written. Therefore, in order to eliminate such an inconvenience, there is provided a comparator for detecting whether or not two consecutively inputted address signals A0 and A1 coincide with each other in late-write or double-late write synchronous SRAM.
FIG. 17 is a circuit diagram showing a configuration of such a comparator 70. It is set that one address signal of two address signals ADD inputted consecutively includes data signals a0 to an (where n is an integer of 0 or more), while the other address signal ADD includes data signals b0 to bn. In FIG. 17, comparator 70 includes: an EX-OR gates 71.0 to 71.n; an OR gate 72; inverters 76 and 77; and a latch circuit 78.
Data signals a0 to an are inputted to respective EX-OR gates 71.0 to 71.n at one input nodes thereof. DATA signals b0 to bn are inputted to respective EX-OR gates 71.0 to 71.n at the other input nodes thereof. OR gate 72 is constructed of plural 2-input NOR gates 73, 74, . . . , 3-input NAND gate 75 and others. The reason why many of 2-input NOR gates and a 3-input NAND gates are used is that it is unrealistic in terms of efficiency to use 4-input or more NOR gates and NAND gates. OR gate 72 receives output signals of EX-OR gates 71.0 to 71.n and an output signal thereof is inverted by inverter 76 and the inverted signal is inputted to latch circuit 78 at the data input terminal D. Latch circuit 78 is in a through state during a period when the inverted signal /CLK of clock signal CLK is at H level to output the inverted signal of an input signal, and holds and outputs a signal at a level of a signal inputted directly prior to transition of clock signal /CLK to L level in response to the transition. An output signal of latch circuit 78 is inverted by inverter 77 to become an output signal CT of comparator 74.
In a case where data signals a0 to an and data signals b0 to bn coincide with each other, output signals of EX-OR gates 71.0 to 71.n all assume L level and an output signal of OR gate 72 assumes L level to cause signal CT to be at H level. In a case where data signals a0 to an and data signals b0 to bn do not coincide with each other, an output signal of at least one EX-OR gate of EX-OR gates 71.0 to 71.n assumes H level and an output signal of OR gate 72 assumes H level to cause signal CT to be at L level. In synchronous SRAM, a read operation is switched in response to signal CT.
In prior art comparator 70, however, since OR gate 72 is constructed of NOR gates and NAND gates at multiple stages, a time is longer between when data signals a0 to an and data signals b0 to bn are made firm and when a result of comparison is outputted, having resulted in a problem of a slower operating speed in SRAM.
Accordingly, a main object of the present invention is to provide a semiconductor memory device with a high operating speed.
A semiconductor memory device according to the present invention includes: plural memory cells; a select circuit selecting a memory cell of the plural memory cells according to an address signal captured in response to an leading edge of a clock signal; a write/read circuit performing writing/reading of a data signal to/from a memory cell selected by the select circuit; and a coincidence/non-coincidence detecting circuit detecting whether or not inputted two address signals coincide with each other to output a control signal controlling the write/read circuit on the basis of a result of the detection. The coincidence/non-coincidence detecting circuit includes: a charge circuit for charging a prescribed node to a first potential; plural discharge circuits provided correspondingly to respective plural signals included in an address signal, and each receiving respective corresponding two signals included in inputted two address signals to discharge the prescribed node to a second potential in response to a situation where two signals that each discharge circuit has received are different from each other in logical level; and a signal generating circuit generating the control signal on the basis of a potential of the prescribed node. Therefore, since no necessity arises for use of NOR gates and NAND gates at multiple stages adopted in a prior art practice, a result of the detection of whether or not two address signals coincide with each other can be quickly obtained, thereby enabling a high operation speed in a semiconductor memory device.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.